The M58LT family offers 128Mb and 256Mb non-volatile Secure Flash solutions.

The family features an asymmetrical block architecture and are based on a multi-level cell
technology. The memory array is organized as 131 blocks, and is divided into 8 Mbit banks.
There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter bank
containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords.

Read-While-Write Architecture allows Dual Operations, while programming or erasing in
one bank, read operations are possible in other banks. Only one bank at a time is allowed to
be in program or erase mode.

The device supports Synchronous Burst Read and Asynchronous Read and Page Read
from all blocks of the memory array; at power-up the device is configured for Asynchronous
Read. In Synchronous Burst Read mode, data is output on each clock cycle at frequencies
of up to 52MHz. The Synchronous Burst Read operation can be suspended and resumed.
The device features an Automatic Standby mode. When the bus is inactive during
Asynchronous Read operations, the device automatically switches to the Automatic Standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.

The M58LT family is equipped with several features to increase data protection:

Hardware Protection: all blocks are protected from program and erase operations when the VPP ≤ VPPLK.
A full set of Software Security Features described in a dedicated Application Note.
Please contact your sales representative for further details.
64-bit Unique Device Identifier
2112 bits of User-Programmable OTP memory