By Kurt Sowa
Numonyx Software Product Manager

The JEDEC LPDDR-NVM specification defines a standard way for flash memory and SDRAM to share a bus efficiently. This can result in lower cost (via reduced pin count and smaller die size) and higher performance. As LPDDR-SDRAM provides for low power consumption, this is increasingly popular for power-sensitive mobile devices. The standard (N07-NV1B) is available for free at http://www.jedec.org/download/.

This article discusses software driver development when moving from parallel NOR flash memory to LPDDR2-NVM (also NOR flash). For this article, it is assumed that the system software has an abstracted flash memory interface. This means that there is an API layer (memory technology driver) that translates read, write and erase requests into the appropriate flash interface commands. Platforms today generally follow this model. This implies that software changes are generally constrained to the memory technology driver.

This article also provides an overview of the LPDDR2-NVM command mechanism. It is not the intention of this article to describe the hardware interfaces or to review all the commands and their usage. It is assumed that the memory controller in use supports the LPDDR2-NMV specification. This article is intended to describe the LPDDR2-NMV software command interface. The specifics of reading and writing to NVM hardware registers are left to the user.

Parallel flash memory versus LPDDR2-NVM

For developers familiar with parallel flash memory, the operations for LPDDR2-NVM will be familiar. The key difference is LPDDR2’s use of an overlay window to enter device command and data, rather than writing the command/data sequence directly to the device address and data bus.

Overlay window

TThis first consideration when using LPDDR2-NVM is that an overlay window is used for operations other than array reads. The overlay window is a window that is mapped into the flash address space. The base address of the overlay window is set (and enabled) using the mode registers. Memory-mapped control registers are statically located from the base address within the overlay window. With the overlay window enabled, reads and writes to the overlaid memory address space access to the overlay window rather than the non-volatile memory (NVM) array. Moving the base address allows access to the entire array while the overlay window is enabled.

The overlay window must be aligned on an 8KB address boundary. The overlay window is enabled and disabled using Mode Register 24, and Mode Registers 25 through 27 are used to set the base address. Once the overlay window is enabled, it is accessed like any other section of memory in the array. Reads and writes within the overlay address space and access the overlay window. Reads outside the overlay window access the regular array, and writes are not allowed outside the overlay windows when it is enabled.

Overlay window register content

The overlay window used to manage NVM is defined by the standard. It provides a method for determining what NVM is present and what its characteristics are. It is also used to issue standard NVM commands, such as buffer program, to the device. The organization of the overlay window is described in the following table.

Control registers

The first 64 words of the control registers are read only and contain JEDEC and device-specific configuration information (for example, Manufacturer ID). The control registers starting at the 128-byte offset are used to configure and execute NVM commands (for register offset and size, see the previous table).

The following table describes the NVM commands defined in the specification. These commands are used to program, erase and configure block locking.

The following list describes each of the control registers:

• Command Code Register: Used to set the ID of the command to be executed.
• Command Data Register: Used for any data other than program data that the command requires. It may also be used to read the result of queries.
• Command Address Register: The base address that the command will be executed upon.
• Multipurpose Register: Used for several purposes. For buffer programming operations, it is used to set the number of contiguous bytes to be programmed.
• Command Execute Register (with a value of 0x0001): Used to initiate the command.
• Suspend Register (with a value of 0x0001): Suspends an active write or erase command. Reading the suspend register will return 0x0001 if the device is in the process of suspending, but is not ready for other operations. It will return 0x0000 if the device is suspended, or if the operation is completed. The suspend register only reflects the readiness of the device. To verify the success of the request, the Status Register should be read.
• Abort Register (with a value of 0x0001): Aborts an active write or erase command. Reading the abort register will return 0x0001 if the device is in the process of aborting, but is not ready for other operations. It will return 0x0000 if the device is ready. Aborting an embedded operation will result in the setting of error bits in the status register.
• Status Register: Reports the ready status of the device, along with any error flags. Writing a “1” to a result bit in the status register will clear that bit (internally set bits that reflect the state of an operation cannot be cleared). The possible values for the status register are listed in the following table. When the SR.7 status bit is zero (not ready), the remaining status bits are indeterminate (invalid).

• Program Buffer: Used to store the data for a buffer program. Its size and offset is vendor specific, please refer to the data sheet for the device.

Sample buffer program operation

The following steps demonstrate the use of the command registers in the overlay window to perform a buffer program.

1. Set the offset of the overlay window. Write the offset address to Mode Registers 25 through 27.
2. Enable the overlay window. Write 0x1 to Mode Register 24. Reading 0x1 from Mode register window will confirm that the window is enabled.
3. Set the Command Code for buffered programming. Write 0x00E9 to the Command Code Register.
4. Load the Command Address Register with the starting address for the write command.
5. Load the Multi Purpose Register with the number of data bytes to be programmed. Program buffers are typically aligned to the size of the maximum write buffer size (read at offset 0x0012 of the overlay region). The starting address plus the program byte count should not exceed the aligned buffer size. Buffer program operations will not cross into the next program region, and will not wrap within the program region. Crossing the end of the programming region will result in an abort and error.
6. Write the data to be programmed to the program buffer region in the overlay map.
7. Initiate the buffer program by writing 0x0001 to the Command Execute Register.
8. Poll the Device Ready Bit in the Status Register. The operation can be suspended if necessary.
9. When the operation completes (device ready bit set), check for errors in the Status Register.
10. Disable the overlay window by writing 0x02 to Mode Register 24. As with enabling the overlay window, the overlay window status (enabled = 1, disabled = 0) can be read from bit 0 of Mode Register 24.

Conclusion

Issuing commands to modify LPDDR2-NVM is straightforward, as the sample buffer program operation illustrates. When updating a platform from parallel flash memory to LPDDR2-NMV, software changes can be limited to the low-level memory driver. The sequence of operations is similar, and modifying the commands to use the overlay window instead of the address/data bus is all that is required. Applications, OS and middleware should not require any changes.