Compared to DDR, DDR2 offers extraordinary performance, reduces power consumption, maximizes DRAM throughput, improves signal integrity, and optimizes flexibility. Some of the measurable differences are highlighted in the comparison chart below.
| Feature/Option |
DDR |
DDR2 |
DDR2 Advantage |
| Package |
66-pin TSOP
54-, 60-ball FBGA |
60-, 84-ball FBGA
63-ball FBGA DDP |
Enables better electrical performance and speed, dual die package enables higher densities |
Voltage (core and I/O)
Low volt |
2.5V-2.6V
N/A |
1.8V
1.55V |
Reduces memory system power demand
DDR2 offers a low voltage solution |
| Densities |
256Mb to 1Gb |
256Mb to 4Gb |
High-density components enable large memory subsystems with fewer chip counts |
| Internal banks |
4 |
4 and 8 |
1Gb and higher density DDR2 devices have 8 banks for better performance |
| Prefetch (MIN WRITE burst) |
2 |
4 |
Enables faster clock rates |
| Data rate (MT/s per pin) |
333
400
667
800 |
533
667
800
1066 |
Migration to higher data bandwidth |
READ latency
Additive latency (posted CAS) |
2, 2.5, 3 CLK
N/A |
CL + AL
CL=3, 4, 5, 6, 7
AL options
0, 1, 2, 3, 4, 5, 6 |
Eliminating one-half clock settings helps speed internal DRAM logic and simplify timing
Mainly used in server applications to improve command bus efficiency |
| WRITE latency |
1 clock |
READ latency - 1 |
Improves command bus efficiency |
| DQ bus termination |
Motherboard parallel to Vtt |
DRAM on-die termination (ODT), optional on-motherboard termination |
ODT for both memory and controller improves signaling, lowers power, and reduces system costs |
| Data strobes |
Single-ended |
Differential or single-ended |
Improves system timing margin by reducing strobe crosstalk |
| Modules |
184-pin DIMM
200-pin SODIMM |
240-pin SODIMM
- unbuffered
- registered
- fully buffered
200-pin SODIMM |
Improved layout, more form factors, and power delivery design |